In multi-processor systems (whether multi-chip or multi-core on a single chip), processors (i.e., physical CPUs or CPU cores, or logical CPUs where simultaneous multithreading is supported on a processor) generally have memory-mapped data areas, known as per-CPU private data areas (PRDAs). Generally, access to variables in a PRDA should be fast and should not be preempted (i.e., interrupted and resumed at a later point in time), since a system software (e.g., a hypervisor) accesses data in the PRDA frequently on performance critical paths.
Some processor architectures have instructions that are inherently atomic when accessing a PRDA to read and/or modify the PRDA. Software written for processor architectures that support atomic instructions generally are written assuming that PRDA accesses will not be interrupted. When software is ported from an architecture that supports these atomic instructions to an architecture that does not support such instructions, the assumption that PRDA accesses will not be interrupted may no longer be true.